The present application relates to amplifiers, and more particularly to amplifiers that have a reduced power consumption.
Audio amplifiers are well known and are used extensively to amplify audio signals. Designing an audio amplifier generally requires balancing two competing concerns. The first concern is fidelity which relates to the accuracy with which the audio amplifier reproduces the sounds contained in the audio signal. The second concern is power efficiency, which relates to the power consumption of the audio amplifier under various operating conditions.
FIG. 1 is a block diagram of an audio amplifier 10, as known in the prior art. Digital-to-analog converter (DAC) 12 converts the digital audio signal Ddig to an analog audio signal. The converted audio signal is applied to a class AB amplifier 14. The amplified audio signal is applied to speaker 16 via AC coupling capacitor 18. As is well known, amplifier 14 has a relatively low efficiency, thus rendering this amplifier undesirable for handheld portable devices which often have a limited battery life and/or internal cooling capacity.
FIG. 2 is a functional block diagram of a conventional analog class D audio amplifier 20. Class D audio amplifier 20 is generally more efficient than class AB amplifier 14 shown in FIG. 1. The fidelity of class D audio amplifier 20 can be comparable to that of Class AB audio amplifier 14 depending on variables such as switching frequency, thermal noise of resistors 24 and 50, noise of amplifier 28, noise and distortion of signal generator 36, noise of comparator 34, the loop delay and the blanking time of driver 40.
DAC 12 converts the digital audio signal Ddig to an analog audio signal which is subsequently amplified by operational amplifier (opamp) 22. Opamp 22 supplies the amplified audio signal to integrator 26 via resistive load 24. Integrator 26 includes an opamp 28 and a feedback capacitor 30. The output signal of integrator 26 is supplied to one of the input terminals of comparator 34. The other input terminal of comparator 34 receives a sawtooth or triangular waveform generated by sawtooth/triangular waveform generator 36. Comparator 34 and sawtooth/triangular waveform generator 36 together form a natural frequency sampling module 32 that generates a pulse-width modulated (PWM) signal. The frequency of the sawtooth/triangular waveform is usually at least 10 times higher than the maximum audible frequency included in the analog audio signal.
Logic and pre-driver 38 converts the received PWM signal into signals suitable for use by driver 40. In some embodiments, driver 40 is single-ended and includes a switch, such as a transistor and the like, that switches power to low-pass filter 44. Such a switch is opened and closed based on the signals received from logic and pre-driver 38. The output signal of driver 40 is applied to low pass filter 44 and is also fed back to integrator 26 via resistor 50. Low-pass filter 44 removes the switching harmonics from the signal it receives via driver 40. Low-pass filter 44 is shown as including an inductor 46 and a capacitor 48. Signal OUT generated by driver 40 is delivered to speaker 16.
FIG. 3 is a block diagram of driver 40 coupled to low-pass filter 44 and speaker 16. Switches 52 and 54 are controlled by signals POS and NEG received from logic and pre-driver 38. To apply a positive pulse to speaker 16, switch 52 is turned on and switch 54 is turned off. To apply a negative pulse to speaker 16, switch 54 is turned on and switch 52 is turned off. Inductor 46 together with capacitor 48 form a low-pass filter that attenuate the high frequency signal components. An AC coupling capacitor 82 can be connected in series with speaker 16 to eliminate a direct current (DC) component of the signal applied to speaker 16.
FIG. 4 is a timing diagram of the input signals received and output signal generated by comparator 34. Sinusoidal signal 62 represents the input signal received from integrator 26. Sawtooth signal 64 represents the signal generated by waveform generator 36. Signal 66 represents the output signal of comparator 34 and is a pulse-width modulated (PWM) signal. The duty cycle of PWM signal 66 is determined by the amount of time that the magnitude of signal 62 is greater than the magnitude of signal 64. The period of PWM signal 66 is determined by the period of signal 64.